gate delay中文是什么意思

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中文翻译
造句

门信号延迟
门延迟
选通延迟

gate gate2 n. 1.〔古语〕街道，路〔一般 ...
delay vt. 延迟，拖延，耽搁。 We'll delay th ...
delay gate 延迟门; 延迟闸门脉冲延迟选通脉冲
no delay gate 快速快门
no-delay gate 快速快门
delay gate generator 延迟选通脉冲发生器; 延迟选通脉冲振荡器
delay gate pulse 延迟先通脉冲
gate delay time 门信号延迟时间
gdt gate delay time 门延迟时间
range gate delay line 距离选通延迟线
trigger gate delay 触发门脉冲延迟
trigger-gate delay 触发选通脉冲延迟, 触发门脉冲延迟
unbounded gate delay 门的无界延迟
delay vt. 延迟，拖延，耽搁。 We'll delay the party for two week. 我们要把会期延迟两周。 The train was delayed by heavy snow. 火车因大雪误点了。 vi. 耽搁，耽误，迟误。 It's getting late; don't delay. 时间已晚，别再耽误了。 n. 延迟，拖延，耽搁，耽误。 No more delays, comrades. 同志们，再迟不行了。 admit of on delay 不能耽搁。 without delay 赶快，立刻，马上。 n. -er 延迟器；缓燃剂。
on delay 通电延迟; 正延迟
-gate comb. f. “…门”〔表示丑闻之意，源出Watergate〕;Whitewatergate白水丑闻。
and gate 和门; 与电路; 与门，[台]及闸; 与门，[台]与门; 与门，与门
and not gate 及反闸; 禁止门
and not-gate 与非门; 禁止门
and or not gate 与或非门
and-not gate 与非门; 禁止门,“与-非”门
and-or gate “与或”门
and-or-not gate 与或非门
at the gate 在大门口
gate n. 1.大门，扉，篱笆门，门扇。 2.闸门；城门；洞门；隘口，峡道。 3.【冶金】浇注道，浇口，切口；【无线电】门电路，选通电路，选通脉冲，启开脉冲，时间限制电路。 4.(运动会、展览会等的)门票收入；观众数；入场费。 5.〔英国〕伦敦 Billingsgate, Newgate 等的略称。 6.锯架。 7.电影放映机镜头窗口。 8.〔俚语〕解雇。 a folding gate折叠门，活栅门。 a turnpike gate征收通行税的关卡。 go [pass] through the gate(s) 进门。 enter at a gate从大门进去。 There was a gate of thousands. 观众数以千计。 at the gate(s) of death 奄奄一息。 crash the gate 〔俚语〕擅自入场。 get the gate 〔美国〕被赶出，被解雇。 give sb. the gate 〔美国〕迫令退席；解雇。 keep the gate 守门。 open a gate to [for] 大开方便之门，给…以机会。 the gate of horn 应验的梦兆，角门。 the gate of ivory 不应验的梦兆，牙门〔据神话传说，应验的梦自角门入，不应验的梦自牙门入〕。 vt. 1.在…装门。 2.(英大学)禁止(学生)外出。 3.用门控制。 adj. -less 无门的。 gate2 n. 1.〔古语〕街道，路〔一般作地名用，如 kirkgate〕。 2.〔方言〕方式，方法。

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例句与用法

Trigger gate delay
触发门脉冲延迟
The problem in high speed signal process , such as parasitic parameter and gate delay is also the difficulty hi the research
生成高速，稳定的时钟信号是本课题的目标。高速信号处理所遇到的常见问题，如寄生参数，门电路延迟是设计难点。
Due to the subtle error among different manufacturing equipment , the gate delay of circuits is different and varies in a given scope , which induces the time uncertainty of the waveform
由于制造设备本身存在微小误差，具体门的延时并不相同，而是在一定范围内变化，引起波形变化的时间不确定。
This paper constructs a stable rlc interconnect model based on the first three moments of the node admittance , and discusses its application to interconnect delay and logic gate delay estimation
摘要基于rlc互连树节点导纳的低阶矩构建了一种稳定的互连模型，并讨论了它在互连树延时和逻辑门延时估计中的应用。
When the silicon technology comes to deep sub - micron level , the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency , the allowable errors become smaller , and the influence of the transmission delay gets bigger , which increase the difficulty of the circuit design
在深亚微米制造技术中，芯片互连线延迟超过门延迟，而且随着集成电路工作频率的提高，允许的时序容差变小，传输延迟的影响加大，设计工作难度增加。
An algorithm of path - based timing optimization by buffer insertion is presented . the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation . and heuristic method of buffer insertion is presented to reduce delay . the algorithm is tested by industral circuit case . experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied
提出了一种基于路径的缓冲器插入时延优化算法,算法采用高阶模型估计连线时延,用基于查表的非线性时延模型估计门延迟.在基于路径的时延分析基础上,提出了缓冲器插入的时延优化启发式算法.工业测试实例实验表明,该算法能够有效地优化电路时延,满足时延约束
In this paper an fault simulator for iddt testing is presented , which can detect concurrently the multi - faults . due to the subtle error among equipment manufacturing , the gate delays of circuits are not the same but range within limits . which induces the uncertainty of the waveform transforming time
本文从故障激活的条件入手,利用五值逻辑,对瞬态电流测试中的延时变化进行波形分析和波形计算,采用并发模拟算法,编程实现了一个iddt测试的故障模拟器。实际电路中由于制造工艺的限制,逻辑门的延时并不相同,而是在一定范围内变化,引起波形变化的时间不确定。